The push toward smaller and faster semiconductor devices has resulted in a shift toward the use of copper for making electrical interconnections in integrated circuits. For example, copper offers a number of benefits over aluminum: higher electrical conductivity, good resistance to electro-migration, and reduced cross talk and propagation delays at higher interconnect densities. The fabrication of copper interconnects are not without difficulties, however.
For instance, when copper is etched, it tends to be redeposited elsewhere on the semiconductor device, or in the deposition chamber. Copper atoms also readily diffuse into silicon-containing dielectric layers. The contamination by copper in unwanted locations can degrade or destroy the performance of microelectronic devices in the integrated circuit.
One way to reduce the problems with copper etching and diffusion is to deposit an underlying barrier layer to block the migration of copper atoms into other components of the semiconductor. To facilitate the adhesion of copper to the diffusion barrier, a seed layer of copper is deposited over the diffusion barrier, followed by the deposition of a second thicker copper-conducting layer over the copper seed layer.
The requirement for a diffusion barrier layer when using copper-containing interconnects introduces another problem. Because the barrier layer occupies a portion of the space in the interconnect, the thickness of the copper seed layer deposited over the barrier layer in the interconnect must be reduced. Moreover, as the dimensions of interconnects shrink with each decrease in node size, so too does the thickness of the copper seed layer.
Depositing a thin metal seed layer is problematic, however. For instance, conventional physical vapor deposition (PVD) processing tools tend to deposit the copper seed layer too rapidly making it difficult to control the layer's thickness. Conventional PVD processes also do not provide a uniform and conformal coating of the copper seed layer inside the interconnect. Typically, the sidewalls of the interconnect have a smaller thickness of the copper seed than the bottom of the interconnect. Additionally, conventional PVD processes can produce an overhang of copper around the top edge of the interconnect. An overhang can exacerbate the inadequate deposition of copper seed on the sidewalls and in some cases pinch off the opening of the interconnect, resulting in a void formation in the interconnect.
Conventional PVD processes also tend to deposit more copper seed on central portions of a wafer substrate than at the edge of the wafer. Consequently the effects of poor sidewall coverage and overhangs will vary for integrated circuits fabricated on different locations of a wafer. This, in turn, can cause undesirable variations in the performance of the integrated circuits built on different areas of the wafer.
Accordingly, what is needed in the art is a method and system for manufacturing interconnects having uniformly conformal, thin, and continuous interconnect metal seed layers, while avoiding the above-discussed disadvantages associated with conventional methods and systems for forming such layers.